1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method of manufacturing the same, and more particularly to a structure of a non-volatile semiconductor memory device and a method of manufacturing the same, wherein reduction in thickness of an insulating film in the vicinity of a peripheral edge of an element-isolating insulating film can be prevented, while the occurrence of crystal defect attributable to expansion of the element-isolating insulating film can be prevented.
2. Description of the Background Art
Conventionally, a Shallow Trench Isolation (STI) for increasing the density of a non-volatile semiconductor memory device is known. This STI is implemented by forming a trench in a semiconductor substrate, filling it with an insulating film such as a silicon oxide film, and planarizing that insulating film.
FIG. 30 shows a cross-sectional view of a conventional non-volatile semiconductor memory device employing the aforementioned STI.
As shown in FIG. 30, the non-volatile semiconductor memory device includes a peripheral circuit portion and a memory cell portion. A trench for element-isolation 29 and a silicon oxide film 21 are formed on the main surface of a semiconductor substrate 1 in the peripheral circuit portion, and a trench for element-isolation 3 and a silicon oxide film 21 are formed on the main surface of semiconductor substrate 1 of the memory cell portion. A nitrided silicon layer 25 is formed on the wall surfaces of trenches 3 and 29.
In the memory cell portion, there is formed a memory cell transistor having a floating gate electrode 8 formed above the main surface of semiconductor substrate 1 with a thermal oxide film 4 interposed, an insulating film 9, and a control gate electrode 35.
Floating gate electrode 8 is formed of a doped polysilicon film 6, and control gate electrode 35 has a doped polysilicon film 10 and a WSi film 11. A silicon oxide film 12 is formed on control gate electrode 35.
In the peripheral circuit portion, there is formed an MOS (Metal Oxide Semiconductor) transistor having a gate electrode 13 formed above the semiconductor substrate 1 with a thermal oxide film 5 interposed. The gate electrode 13 has doped polysilicon film 10 and WSi film 11. The silicon oxide film 12 is also formed on gate electrode 13.
An interlayer insulating film 14 is formed to cover the above-mentioned memory cell transistor and MOS transistor. The interlayer insulating film 14 has a contact hole 15, in which a W plug 16 is formed. On interlayer insulating film 14, an interconnection film 17 is formed, which is electrically connected with W plug 16.
Referring now to FIGS. 31 to 41, a method of manufacturing the non-volatile semiconductor memory device having the aforementioned structure will be described.
As shown in FIG. 31, a thermal oxide film 30 is formed on the main surface of semiconductor substrate 1, and a silicon nitride film 18 is formed on the thermal oxide film 30. A photoresist 34 is formed to have a predetermined shape on silicon nitride film 18 by photolithography. Silicon nitride film 18 and thermal oxide film 30 are etched using photoresist 34 as a mask.
After removal of photoresist 34, semiconductor substrate 1 is etched using silicon nitride film 18 as a mask to form trench 3 as shown in FIG. 32. The inner wall of trench 3 is nitrided with NO, N2O or the like to form nitrided silicon layer 25.
Then, silicon oxide film 21 is deposited to fill in trench 3 as shown in FIG. 33. Thereafter, as shown in FIG. 34, CMP (Chemical Mechanical Polishing) is performed for silicon oxide film 21.
As shown in FIG. 35, silicon oxide film 21 is then wet-etched by a predetermined amount with hydrofluoric acid, silicon nitride layer 18 is removed by hot phosphoric acid, and thermal oxide film 30 is removed by hydrofluoric acid.
Then, a thermal oxide film 4 is formed, which will serve as a tunnel oxide film in the memory cell portion. At this point as shown in FIG. 36, in a region 40 where nitrided silicon layer 25 appears on the surface of semiconductor substrate 1, thermal oxide film 4 becomes locally thin, so that a thin portion 4a is formed in thermal oxide film 4 at the periphery of the element-isolating oxide film.
On the thermal oxide film 4, a doped polysilicon film 6 is formed, and on the doped polysilicon film 6, a photoresist 36 is formed. Doped polysilicon film 6 is etched using this photoresist 36 as a mask, as shown in FIG. 37.
After removal of photoresist 36, insulating film 9 is deposited on doped polysilicon film 6, and a photoresist 37 is formed to have a predetermined shape on insulating film 9 as shown in FIG. 38. Being etched using this photoresist 37 as a mask, insulating film 9, doped polysilicon film 6, and thermal oxide film 4 on the peripheral circuit portion are removed.
Then, as shown in FIG. 39, thermal oxide film 5 is formed on the peripheral circuit portion. At this point, in a region where nitrided silicon layer 25 appears on the surface of semiconductor substrate 1, thermal oxide film 5 becomes locally thin, so that a thin portion is formed in thermal oxide film 5 at the periphery of the element-isolating oxide film.
Doped polysilicon film 10, WSi film 11 and silicon oxide film 12 are deposited on thermal oxide film 5 and insulating film 9. As shown in FIG. 39, a photoresist 38 is formed to have a predetermined shape on silicon oxide film 12, and silicon oxide film 12 is etched using photoresist 38 as a mask.
After removal of photoresist 38, WSi film 11 and doped polysilicon film 10 are etched using silicon oxide film 12 as a mask. Accordingly, as shown in FIG. 40, control gate electrode 35 in the memory cell portion and gate electrode 13 of MOS transistor in the peripheral circuit portion are formed.
Thereafter, as shown in FIG. 41, a photoresist 39 covering the peripheral circuit portion is formed, and insulating film 9 and doped polysilicon film 6 in the memory cell portion are etched using photoresist 39 as a mask. Accordingly, floating gate electrode 8 of the memory cell portion is formed.
Then, following a prescribed impurity implantation, interlayer-insulating film 14 is deposited. In this interlayer insulating film 14, a contact hole 15 is formed, in which the W plug is formed. Interconnection film 17 is formed on interlayer insulating film 14. Through the above steps, the non-volatile semiconductor memory device shown in FIG. 30 is formed.
When a thermal oxidation process is performed for forming the above mentioned thermal oxide film 4 and the like, oxidation may possibly develop from the inner wall of the trench, and the filled silicon oxide film 21 may undesirably expand. When silicon oxide film 21 expands, a large stress is exerted onto semiconductor substrate 1 to adversely increase crystal defect density in semiconductor substrate 1.
In the non-volatile semiconductor memory device shown in FIG. 30, however, nitrided silicon layer 25 is formed on the inner walls of trenches 3 and 29, so that the aforementioned expansion of silicon oxide film 21 can be prevented, and thus increase in crystal defect density in semiconductor substrate 1 can be prevented.
On the other hand, since nitrided silicon layer 25 reaches up to the main surface of semiconductor substrate 1 as shown in FIG. 35, upon formation of thermal oxide film 4 in the subsequent step, the growth of thermal oxide film 4 is inhibited on nitrided silicon layer 25. Therefore, as shown in FIG. 36, the thermal oxide film 4 is reduced in thickness on nitrided silicon layer 25, resulting in formation of thin portion 4a as previously mentioned.
Presence of such thin portion 4a lowers a breakdown voltage in this portion, for example, to make it difficult to ensure the desired electric characteristics and reliability.
The present invention is made to solve the above mentioned problem, and its objet is to improve the electric characteristics and reliability of a non-volatile semiconductor memory device in which a nitrided silicon layer is formed on the inner wall of a trench for element-isolation.
A non-volatile semiconductor memory device in accordance with the present invention includes: a semiconductor substrate having a main surface; a plurality of trenches for element-isolation formed in the semiconductor substrate; a nitrided silicon layer formed along a wall surface of the trench; a first insulating film for element-isolation formed in the trench; a second insulating film extending from the aforementioned main surface located at the periphery of the nitrided silicon layer onto the nitrided silicon layer, the thickness of a portion located on the nitrided silicon layer being at least the thickness of a portion located at the periphery of the nitrided silicon layer; a floating gate electrode formed on the second insulating layer; and a control gate electrode on the floating gate electrode with a third insulating film interposed.
The formation of the nitrided silicon layer along the wall surface of the trench as mentioned above can prevent oxidation and resulting expansion of the first insulating film for element-isolation, and can decrease the crystal defect density in the semiconductor substrate. Furthermore, as the thickness of the second insulating film located on the nitrided silicon layer is made the same or thicker than the thickness of the second insulating layer located at the periphery of the nitrided silicon layer, the desired electric characteristics and reliability on the nitrided silicon layer can be ensured.
The aforementioned trench is formed by etching the semiconductor substrate using at least a part of the floating gate electrode as a mask.
The trench is formed self-aligned to the floating gate electrode in this manner, so that the high density integration of the non-volatile semiconductor memory device can be attained.
The aforementioned nitrided silicon layer is preferably formed by nitriding the wall surface of the trench after oxidation thereof.
Therefore, before formation of the nitrided silicon layer, the oxide film of a desired thickness can be formed in advance at the upper end portion of the trench, under which the nitrided silicon layer can be formed. As a result, the growth of the second insulating film, that would be otherwise held back by the nitrided silicon layer, is ensured. Further, the thickness of the second insulating film located on the nitrided silicon layer can be made equal to or larger than the thickness of the second insulating film located at the periphery of the nitrided silicon layer. It is noted that when a bird""s beak caused by oxidation of the wall surface of the trench is extended onto the region where the nitrided silicon layer is to be formed, the thickness of the second insulating film located on the nitrided silicon layer can be made equal to or larger than the thickness of the second insulating film located at the periphery of the nitrided silicon layer.
The above mentioned non-volatile semiconductor memory device includes a memory cell portion, in which memory cell transistors are formed, and a peripheral circuit portion, in which peripheral circuitry is formed, for controlling the operation of the memory cell transistor. The aforementioned trench is formed in the memory cell portion.
Accordingly, while the density of the element (memory cell transistor) in the memory cell portion can be increased, crystal defect can be prevented, and the electric characteristics and reliability in the memory cell portion can be improved.
A fourth insulating film for element-isolation may be formed in the aforementioned peripheral circuit portion by selective oxidation of the semiconductor substrate (LOCOS: Local Oxidation of Silicon). This enables the fourth insulating film to be formed in simple process as compared with trench isolation.
The non-volatile semiconductor memory device includes a memory cell portion, a peripheral circuit portion, and an MOS (Metal Oxide Semiconductor) transistor in the peripheral circuit portion. In this case, the above mentioned trench includes a first trench formed in the memory cell portion, and a second trench formed in the peripheral circuit portion, and the nitrided silicon layer includes first and second nitrided silicon layers respectively formed along the wall surfaces of the first and second trenches. The first insulating film is formed in the first trench, and a fourth insulating film for element-isolation is formed in the second trench. The second insulating film is formed at the periphery of the first trench, and a fifth insulating film is formed at the periphery of the second trench. The second insulating film extends from the main surface located at the periphery of the first nitrided silicon layer onto the first nitrided silicon layer, and the thickness of a portion located on the first nitrided silicon layer in the second insulating film is equal to or larger than the thickness of a portion located on the main surface of the periphery of the first nitrided silicon layer in the second insulating film. The fifth insulating film extends from on the main surface located at the periphery of the second nitrided silicon layer onto the second nitrided silicon layer, and the thickness of a portion located on the second nitrided silicon layer in the fifth insulating film is at least the thickness of a portion located on the main surface of the periphery of the second nitrided silicon layer in the fifth insulating film. A gate electrode of the MOS transistor is formed on the fifth insulating film.
The trench isolation structure is formed in both of the memory cell portion and the peripheral circuit portion in this manner, so that in both of the memory cell portion and the peripheral circuit portion, crystal defect can be prevented while the density of the elements is increased, and in addition, the electric characteristics and reliability can be improved.
A method of manufacturing a non-volatile semiconductor device in accordance with the present invention includes the following steps. A mask film including a first conductive film is formed on a main surface of a semiconductor substrate with a first insulating film interposed. This mask film is used to etch the semiconductor substrate, so that a plurality of trenches for element-isolation are formed. A wall surface of the trench is oxidized. After this oxidation, the wall surface of the trench is nitrided to form a nitrided silicon layer extending along the wall surface of the trench. A second insulating film for element-isolation is formed in the trench. By reducing the thickness of the mask film, the first conductive film is exposed. A second conductive film is formed above the first conductive film with a third insulating film interposed. By patterning the second conductive film, the third insulating film and the first conductive film, a floating gate electrode and a control gate electrode are formed.
Since the wall surface of the trench is oxidized after formation of the first insulating film and the wall surface of the trench is nitrided thereafter, the nitrided silicon layer can be formed under the first insulating film. Therefore, unlike the conventional example in which the oxide film is grown on the nitrided silicon layer, the first insulating film of a desired thickness can be formed on the nitrided silicon layer. As a result, the electric characteristics and reliability of the non-volatile semiconductor memory device can be improved as stated above.
The step of oxidizing the wall surface of the trench preferably includes the step of forming an oxide film on the wall surface of the trench such that it reaches the first insulating film. In this case, the step of forming the nitrided silicon layer preferably includes the step of forming the nitrided silicon layer such that it extends along the trench, in the region located on the periphery of the oxide film and under the first insulating film, by nitriding the wall surface of the trench from on the oxide film.
The wall surface of the trench is nitrided from the aforementioned oxide film formed on the wall surface of the trench in advance in this way, so that the nitrided silicon layer can be formed at the periphery of the oxide film and under the first insulating film. At this point, a bird""s beak can be formed on the region where the nitrided silicon layer is to be formed, in which case, the thickness of the first insulating film located on the nitrided silicon layer can be made equal to or larger than the thickness of the first insulating film located at the periphery of the nitrided silicon layer.
The floating gate electrode may have a third conductive film stacked on the first conductive film. In this case, the step of forming the second conductive film includes the steps of forming on the first conductive film the third conductive film to extend over the second insulating film, and forming the third insulating film to cover the third conductive film. Furthermore, the step of forming the floating gate electrode and the control gate electrode includes the step of forming the floating gate electrode and the control gate electrode, by patterning the second conductive film, the third insulating film, the third conductive film and the first conductive film.
By stacking the third conductive film on the first conductive film as mentioned above, the floating gate electrode can be formed in a stacked structure of the conductive films. Furthermore, by forming the first and third conductive films separately, the first and third conductive films can be formed to a desired thickness, while a good state of an interface with other elements in contact with the first and third conductive films can be kept. Still further, by adjusting concentration of the impurity to be doped into the first and third conductive films properly, a desired resistance value of the floating gate electrode can be attained. In addition, since the third conductive film extends over the second insulating film, the surface area of the third conductive film can be made greater than the surface area of the first conductive film, and the surface area of the floating gate electrode can be increased. Therefore, the coupling ratio of the floating gate electrode to control gate electrode can be improved.
The above mentioned non-volatile semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The trench is formed in the memory cell portion, and a fourth insulating film for element-isolation is formed in the peripheral circuit portion. In this case, the step of forming the mask film includes the step of forming the mask film after formation of the fourth insulating film in the peripheral circuit portion. Furthermore, the aforementioned fourth insulating film may be formed by selectively oxidizing the semiconductor substrate.
The fourth insulating film for element-isolation is formed in the peripheral circuit portion before formation of the memory cell portion, so that proper element-isolating structure can be respectively selected in the peripheral circuit portion and the memory cell portion. Furthermore, by forming the fourth insulating film in the peripheral circuit portion, for example, by LOCOS process, the fourth insulating film can be formed in a simple process as compared with the trench isolation.
The above mentioned non-volatile semiconductor memory device includes a memory cell portion, a peripheral circuit portion, and an MOS transistor in the peripheral circuit portion, the trench includes a first trench formed in the memory cell portion and a second trench formed in the peripheral circuit portion, the nitrided silicon layer includes a first and second nitrided silicon layers respectively formed along the wall surfaces of the first and second trenches, and the second insulating film is formed in the first and second trenches. In this case, the step of forming the trench includes the step of forming the second trench in the peripheral circuit portion along with forming the first trench in the memory cell portion. The step of oxidizing the wall surface of the trench includes the step of oxidizing the wall surfaces of the first and second trenches. The step of forming the nitrided silicon layer includes the step of forming the first and second nitrided silicon layers along the wall surfaces of the first and second trenches. The step of forming the second insulating film includes the step of forming the second insulating film in the first and second trenches. The step of forming the floating gate electrode and the control gate electrode includes the step of forming the floating gate electrode and the control gate electrode in the memory cell portion along with forming a gate electrode of the MOS transistor in the peripheral circuit portion, by patterning the second conductive film, the third insulating film and the first conductive film.
The trench isolation region is formed in the memory cell portion and the peripheral circuit portion at the same time in this manner, so that the step can be simplified as compared with formation of isolation region in each portion in different steps. Furthermore, the nitrided silicon layer is formed in the wall surfaces of both the memory cell portion and the peripheral circuit portion by the aforementioned technique, so that the electric characteristics and reliability for the elements both in the memory cell portion and in the peripheral circuit portion can be improved while increase in crystal defect density can be prevented.
The floating gate electrode and the gate electrode of the above-mentioned MOS transistor may have a third conductive film on the first conductive film. In this case, the step of forming the second conductive film includes the steps of forming on the first conductive film the third conductive film to extend over the second insulating film, and forming the third insulating film to cover the third conductive film, and the step of forming the floating gate electrode and the control gate electrode includes the step of forming the floating gate electrode and the control gate electrode in the memory cell portion along with forming the gate electrode of the MOS transistor in the peripheral circuit portion, by patterning the second conductive film, the third insulating film, the third conductive film and the first conductive film.
In this case, while the coupling ratio of the floating gate electrode to the control gate electrode can be improved, the gate electrode of the MOS transistor in the peripheral circuit portion can be provided in a multi-layered structure including the first to third conductive layers.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.